1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which is capable of reducing the number of data drive integrated circuits (ICs) to curtail a production cost.
2. Discussion of the Related Art
In recent informationized society, displays are visual information transfer media, whose importance is emphasized than ever. Various flat panel displays have been developed.
These flat panel displays may be, for example, a liquid crystal display (LCD), field emission display (FED), plasma display panel (PDP), electroluminescence (EL) display, organic light emitting diode (OLED), and the like.
The liquid crystal display, among the flat panel displays, is on a trend of being applied within a wider range owing to its characteristics of lightness, thinness, low power consumption driving, etc. According to such a trend, the liquid crystal display has been used in a portable computer such as a notebook personal computer (PC), an office automation device, an audio/video device, an indoor/outdoor advertisement display device, etc., and been rapidly advanced toward a larger size and higher resolution owing to recent security of mass production technologies and recent results of research and development.
In general, a liquid crystal display device is adapted to adjust light transmittance of liquid crystal cells according to a video signal so as to display an image. This liquid crystal display device basically includes a liquid crystal display panel including liquid crystal cells arranged between two glass substrates in matrix form for displaying an image, a backlight unit for emitting light to the liquid crystal display panel, and a driving circuit for supplying a drive signal to drive the liquid crystal display panel.
FIG. 1 schematically shows the configuration of a conventional liquid crystal display device.
Referring to FIG. 1, the conventional liquid crystal display device, denoted by reference numeral 1, includes a liquid crystal display panel 10 including pixel areas formed respectively in areas defined by a plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn, a gate driver 30 for sequentially supplying a gate drive signal to the gate lines GL1 to GLm, a data driver 20 for supplying video data Red, Green and Blue inputted thereto to the data lines DL1 to DLn synchronously with the gate drive signal, and a timing controller 40 for converting and arranging external video data R, G and B and supplying the resulting video data to the data driver 20, and controlling the driving of the gate driver 30 and data driver 20.
Although not shown, the liquid crystal display device further includes a backlight unit for emitting light to the liquid crystal display panel 10, an inverter for applying a voltage and current to the backlight unit, a reference gamma voltage generator for generating a reference gamma voltage and supplying it to the data driver 20, and a voltage generator for generating a drive voltage to drive each component and supplying a common voltage Vcom to a common electrode of the liquid crystal display panel 10.
The liquid crystal display panel 10 includes a transistor array substrate and a color filter array substrate bonded to face each other, a spacer for keeping a cell gap between the two array substrates constant, and a liquid crystal filled in a space provided by the spacer.
The liquid crystal display panel 10 further includes thin film transistors (TFTs) formed respectively in pixel areas defined by the m gate lines GL1 to GLm and the n data lines DL1 to DLn, and pixel cells connected respectively to the TFTs.
Each TFT supplies an analog video data signal from a corresponding one of the data lines DL1 to DLn to a corresponding one of the pixel cells in response to a gate drive signal from a corresponding one of the gate lines GL1 to GLm.
Each pixel cell can be equivalently expressed as a liquid crystal capacitor Clc because it is provided with a common electrode facing via the liquid crystal, and a pixel electrode connected to the corresponding TFT. This pixel cell includes a storage capacitor Cst for maintaining an analog video data signal charged on the liquid crystal capacitor Clc until the next analog video data signal is charged thereon. The common voltage Vcom is supplied to the common electrode of the pixel cell.
Each TFT has a gate electrode connected to a corresponding one of the gate lines GL1 to GLm, a source electrode connected to a corresponding one of the data lines DL1 to DLn, and a drain electrode connected to the pixel electrode of the corresponding pixel cell.
On the color filter array substrate of the liquid crystal display panel 10, red (R), green (G) and blue (B) color filters are vertically striped and formed in matrix form.
The timing controller 40 arranges video data R, G and B inputted from a digital video card on a frame-by-frame basis and supplies the arranged video data to the data driver 20.
Also, the timing controller 40 generates a data control signal DCS and a gate control signal GCS using a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronous signals Hsync and Vsync externally inputted thereto, and applies the generated data control signal DCS and gate control signal GCS respectively to the data and gate drivers 20 and 30 to control the driving timings thereof.
Here, the data control signal DCS includes a source shift clock SSC, source start pulse SSP, polarity control signal POL and source output enable signal SOE, and the gate control signal GCS includes a gate start pulse GSP, gate shift clock GSC and gate output enable signal GOE.
The gate driver 30 includes a shift register for sequentially generating a gate drive signal (gate scan pulse) in response to the gate control signal GCS from the timing controller 40.
This gate driver 30 sequentially applies the gate drive signal to the gate lines GL1 to GLm in response to the gate control signal GCS from the timing controller 40, so as to turn on the TFTs connected respectively to the gate lines GL1 to GLm. At this time, the gate driver 30 determines a high-level voltage and low-level voltage of the gate drive signal depending on a gate high voltage VGH and gate low voltage VGL inputted thereto.
The data driver 20 supplies analog video data signals to the data lines DL1 to DLn at intervals at which the gate drive signal is supplied, in response to the data control signal DCS supplied from the timing controller 40. At this time, the data driver 20 inverts the polarities of the analog video data signals to be supplied to the data lines DL1 to DLn in response to the polarity control signal POL.
In the above-mentioned conventional liquid crystal display device, red (R), green (G) and blue (B) color filters formed in the liquid crystal display panel are vertically striped and three horizontally adjacent red (R), green (G) and blue (B) color pixels are combined to constitute one unit pixel. As a result, the liquid crystal display device needs 3×n data lines DL and 1×m gate lines to express m×n resolution.
A large number of data drive ICs are required to supply video data to the 3×n data lines DL. However, the data drive ICs are costly, resulting in an increase in manufacturing cost of the liquid crystal display device.